In a typical block of memory such as random access memory (RAM), memory cells are arranged in rows and columns, where the memory cells in each row are accessed by energizing a word-line shared by those memory cells, where each different row has its own unique word-line and each word-line has its own unique address in the memory block.
For example, for a block of memory having 64 rows of memory cells and 64 corresponding word-lines, each of the 64 different word-lines would typically have its own unique 6-bit address. A particular row of memory cells is accessed by applying the 6-bit address of the row's corresponding word-line to an address decoder that is connected to all 64 word-lines. The address decoder decodes (i.e., interprets) the 6-bit address and energizes the corresponding word-line to access the particular row of memory cells. In a typical memory block, no more than one word-line is allowed to be energized at a time.
FIG. 1 shows a block diagram of a conventional address decoder 100 for decoding a 6-bit word-line address (A5 A4 A3 A2 A1 A0) to energize one of 64 word-lines WL<63:0> in a block of memory. Address decoder 100 has three 2-bit decoders 102-1, 102-2, and 102-3 and sixteen word-line drivers 104-1 to 104-16, only two of which are shown in FIG. 1.
Two-bit decoder 102-1 receives (least-significant) address bits A0 and A1 and generates four decoded bit values DEC0–DEC3, which are applied to the D3–D0 inputs of each of the 16 word-line drivers 104. The following logic table shows the decoding processing implemented by 2-bit decoder 102-1.
TWO-BIT DECODER LOGICA1A0DEC3DEC2DEC1DEC0000001010010100100111000
Two-bit decoder 102-2 receives address bits A2 and A3 and generates four decoded bit values DEC4–DEC7. Similarly, two-bit decoder 102-3 receives (most-significant) address bits A4 and A5 and generates four decoded bit values DEC11–DEC8. Two-bit decoders 102-2 and 102-3 implement logic similar to that of 2-bit decoder 102-1.
In addition to receiving decoded bit values DEC0–DEC3, each word-line driver 104 receives enable signal ENABLE (at its EN input) and a unique combination of one of decoded bit values DEC4–DEC7 (at its D74 input) and one of decoded bit values DEC8–DEC11 (at its D118 input) and uses those input signals to control four word-line drive signals WL for a different set of four word-lines in the 64-word-line memory block. As shown in FIG. 1, word-line driver 104-1 receives the two-bit combination of decoded bit values DEC8 and DEC4 and generates four word-line drive signals WL<3:0> that are applied to the first set of four word-lines in the memory block. Similarly, word-line driver 104-16 receives the two-bit combination of decoded bit values DEC11 and DEC7 and generates four word-line drive signals WL<63:60> that are applied to the last set of four word-lines in the memory block. The 14 other two-bit combinations of DEC7–DEC4 and DEC11–DEC 8 are input to the other 14 word-line drivers 104 (not shown in FIG. 1) to generate the remaining word-line drive signals WL<59:4> for the remaining 56 word-lines in the memory block.
For each possible 6-bit address, only one of the 16 unique two-bit combinations applied to the 16 different word-line drivers 104 will have a value of (11). The particular word-line driver 104 that receives this combination at its D118 and D74 inputs will energize one of its four word-line drive signals WL (as determined by the four decoded bit values DEC3–DEC0). Each of the other 15 word-line drivers 104 will receive a different two-bit combination (i.e., (10), (01), or (00)) at its D118 and D74 inputs and will therefore not energize any of its four word-line drive signals WL.
A word-line driver 104 is not able to energize any of its word-line drive signals WL if the ENABLE signal is low. The ENABLE signal is typically controlled such that it is driven high only after the rest of the processing in address decoder 100 has settled, in order to prevent more than one word-line drive signal WL from being energized at the same time.
FIG. 2 shows a schematic diagram of a portion of a prior-art static four-line word-line driver 200, which may be used to implement each word-line driver 104 in FIG. 1. Word-line driver 200 controls four word-line drive signals WL0–WL3 based upon input signals D118, D74, D0–D3, and EN. FIG. 2 shows the circuitry used to control only the first two of the four word-line drive signals WL0 and WL1, which circuitry relies on input signals D0 and D1. Word-line driver 200 also has an analogous set of circuitry that relies on input signals D2 and D3 (in place of input signals D0 and D1) to control word-line drive signals WL2 and WL3. Note that both sets of circuitry share NFETs 210 and 204.
Referring to FIG. 2, if input signals D118 and D74 are both high (i.e., logical 1), then PFETs 202 and 208 are off, and NFETs 204 and 210 are on, which drives node W low (i.e., logical 0). If input signal D0 is also high, then PFET 220 is off, and NFET 218 is on, which allows node W to drive node W0 (at the input of inverter 222) low and therefore the output of inverter 222 high. If input signal EN is also high, then word-line drive signal WL0 at the output of AND gate 226 will also be high, thereby energizing the corresponding word-line.
Alternatively, if input signals D118, D74, and D1 are all high, then PFETs 202, 208, and 216 are off, and NFETs 204, 210, and 214 are on, which drives node W and node W1 (at the input of inverter 224) low and therefore the output of inverter 222 high. If input signal EN is also high, then word-line drive signal WL1 at the output of AND gate 228 will also be high, thereby energizing the corresponding word-line.
FIG. 3 illustrates a pair of signal-timing diagrams 302 and 304 for word-line driver 200 of FIG. 2. Timing diagram 302 corresponds to the selection of word-line drive signal WL0, while timing diagram 304 corresponds to the selection of word-line signal WL1.
At time T0, input signals D118, D74, D1, D0, and EN are all low. According to the circuitry of FIG. 2 and as shown in FIG. 3, at time T0, nodes W, W0, and W1 will be high, and nodes WL0 and WL1 will be low.
At time T1, input signals D118, D74, and D0 go high (e.g., as a result of an appropriate 6-bit address value being applied to the three 2-bit decoders 102 of FIG. 1), while input signals D1 and EN remain low. As a result, the circuitry of word-line driver 200 drives node W low, followed by node W0 being driven low.
At time T2, input signal EN goes high. As a result, the circuitry of word-line driver 200 drives node WL0 high, thereby energizing the corresponding word-line.
Similarly, in timing diagram 304, at time T3, input signals D118, D74, D1, D0, and EN are again all low, and again nodes W, W0, and W1 will be high, and nodes WL0 and WL1 will be low.
At time T4, input signals D118, D74, and D1 go high, while input signals D0 and EN remain low. As a result, the circuitry of word-line driver 200 drives node W low, followed by node W1 being driven low.
At time T5, input signal EN goes high. As a result, the circuitry of word-line driver 200 drives node WL1 high, thereby energizing the corresponding word-line.
Similar timing diagrams could be drawn showing the analogous signal levels associated with selectively driving one of word-lines WL2 and WL3 high using the other half of the circuitry of word-line driver 200 that is not shown in FIG. 2.
As indicated in FIG. 3, the assertion of the enable signal is delayed relative to the assertion of the address bits (e.g., which may be said to occur at times T0 and T3) to give time for the rest of the processing of the address decoder (i.e., the decoding of the address bits in the different 2-bit decoders (e.g., from time T0 to T1) as well as the processing of the resulting decoded bit values within the word-line driver (e.g., from time T1 to T2)) to settle. Note that the timing diagram in FIG. 3 began with all decoded addresses (D118, D74, D1, and D0) low, but any combination of these signals could begin high. If the enable signal were asserted too early, then an undesirable condition could exist where two or more word-lines are energized at the same time.
As shown in FIG. 2, word-line driver 200 has a PFET transistor associated with each decoded-bit input value in each word-line, where the PFETs are used to pull nodes W0 and W1 high if at least one of the corresponding decoded-bit input values is low. For example, at least one of PFETs 202, 208, and 222, associated with word-line WL0, will be on if at least one of decoded-bit input values D118, D74, and D0 is low. Thus, for all four word-lines, word-line driver 200 will have a total of 12 PFETs associated with its six decoded-bit input values (i.e., D0–D3, D74, and D118). Such a static word-line driver occupies a significant amount of layout area and consumes a significant amount of power.
FIG. 4 shows a schematic diagram of a portion of a prior-art dynamic four-line word-line driver 400, which, like static word-line driver 200 of FIG. 2, may be used to implement each word-line driver 104 in FIG. 1. Like word-line driver 200, word-line driver 400 controls four word-line drive signals WL0–WL3 based upon input signals D118, D74, D0–D3, and EN. Like FIG. 2, FIG. 4 shows the circuitry used to control only the first two of the four word-line drive signals WL0 and WL1, which circuitry relies on input signals D0 and D1. Word-line driver 400 also has an analogous set of circuitry that relies on input signals D2 and D3 (in place of input signals D0 and D1) to control word-line drive signals WL2 and WL3. Note that both sets of circuitry share NFETs 402, 404, and 406.
Referring to FIG. 4, if input signals EN, D118, and D74 are all high, then NFETs 402, 404, and 406 are on, which drives node W low. If input signal D0 is also high, then NFET 410 is on, which allows node W to drive node W0 low and therefore node WL0 (at the output of inverter 416) high, thereby energizing the corresponding word-line. Inverter 416 and PFETs 412 and 414 form a feed-back latch that drives node WL0 low if input signal EN goes low.
Alternatively, if input signal D1 is high (instead of input signal D0), then NFET 408 is on, which allows node W to drive node W1 low and therefore node WL1 (at the output of inverter 422) high, thereby energizing the corresponding word-line. Inverter 422 and PFETs 418 and 420 form a feed-back latch that drives node WL1 low if input signal EN goes low.
FIG. 5 illustrates a pair of signal-timing diagrams 502 and 504 for word-line driver 400 of FIG. 4. Timing diagram 502 corresponds to the selection of word-line drive signal WL0, while timing diagram 504 corresponds to the selection of word-line signal WL1.
At time T0, input signals D118, D74, D1, D0, and EN are all low. According to the circuitry of FIG. 4 and as shown in FIG. 5, at time T0, the value at node W will be indefinite (as a node floating between deactivated NFETs), nodes W0 and W1 will be high (as a result of the EN signal turning on PFETs 412 and 418), and nodes WL0 and WL1 will be low.
At time T1, input signals D118, D74, and D0 go high, while input signals D1 and EN remain low, which causes the circuitry of word-line driver 400 to drive node W high (i.e., via PFET 412 and NFET 410).
At time T2, input signal EN goes high, which causes the circuitry of word-line driver 400 to drive node W low (via NFETs 402, 404, and 406) and node W0 low (via NFET 410), which in turn drives node WL0 high (via inverter 416), thereby energizing the corresponding word-line.
Similarly, in timing diagram 504, at time T3, input signals D118, D74, D1, D0, and EN are again all low, and again the value at node W will be indefinite, nodes W0 and W1 will be high, and nodes WL0 and WL1 will be low.
At time T4, input signals D118, D74, and D1 go high, while input signals D0 and EN remain low, which causes the circuitry of word-line driver 400 to drive node W high (i.e., via PFET 22 and NFET 408).
At time T5, input signal EN goes high, which causes the circuitry of word-line driver 400 to drive node W low (via NFETs 402, 404, and 406) and node W1 low (via NFET 408), which in turn drives node WL1 high (via inverter 422), thereby energizing the corresponding word-line.
One of the advantages of dynamic word-line driver 400 over static word-line driver 200 of FIG. 2 is that word-line driver 400 does not have any PFETs associated with any of its decoded-bit input values. Rather, for each word-line WLi, word-line driver 400 has a latch driven by input signal EN, which functions as a pre-charge signal to drive the corresponding node Wi high if input signal EN is in its low pre-charge state.
One of the disadvantages of word-line driver 400 is the possibility of inadvertently driving two (or more) word-lines at the same time. As described previously, under ideal (e.g., noise-free and with sufficient timing margin) circumstances, at most, only one of input signals D0 and D1 will be high at any time.
For example, as shown in timing diagram 302 of FIG. 3, if input signals D118, D74, and D0 are all high, while input signal D1 is low, then asserting input signal EN at time T2 will drive node WL0 high, while node WL1 stays low. Driving input signal EN high also turns off the latches associated with both nodes WL0 and WL1. As a result, nothing in word-line driver 400 is left to ensure that WL1 will stay low. If, for example, a temporary noise glitch occurs in input signal D1 or if D1 is originally high and does not go low before EN goes high, causing a temporary overlap of high decoded addresses, then NFET 408 could turn on, which would enable node W to drive node W1 low, which in turn would drive node WL1 high, thereby resulting in the undesirable situation in which word-lines WL0 and WL1 are simultaneously energized. After the temporary noise glitch disappears from input signal D1 or when D1 goes low from decoding and NFET 408 turns back off, node W1 will be a floating node that could stay low and thereby undesirably keep word-line WL1 energized.